`timescale 1ns/1ns

module tb_SimplePll ();

    // 周期20ns
    parameter CLOCK_PERIOD=20;

    reg sys_clk;
    reg sys_rst_n;

    // output declaration of module SimplePll
    wire clk_100;
    wire clk_100_deg180;
    wire clk_50;
    wire clk_25;

    always #(CLOCK_PERIOD/2) sys_clk=!sys_clk;

    initial begin
        sys_clk<=1'b0;
        sys_rst_n<=1'b0;
        #200 sys_rst_n<=1'b1;
    end

    SimplePll u_SimplePll(
                  .sys_clock      	(sys_clk       ),
                  .sys_rst_n      	(sys_rst_n       ),
                  .clk_100        	(clk_100         ),
                  .clk_100_deg180 	(clk_100_deg180  ),
                  .clk_50         	(clk_50          ),
                  .clk_25         	(clk_25          )
              );

endmodule
